1. Field of the Invention
This invention relates to a through-silicon via (TSV) testing structure, particularly to a through-silicon via (TSV) testing structure with simplifying test procedure.
2. Description of the Prior Art
The system in package (SIP) is one of main packaging techniques at present, because the SIP is able to use more advanced off-line mounted way (such as through-silicon via (TSV) etc.) in semiconductor process. Due to the process miniaturization and limitation of dielectric material, the heap packaging technology of the three-dimensional (3D) stack packaging has already been considered as the key point for making high efficient chip with smaller size. The through-silicon via uses wafer stacking through vertical conduction, in order to reach the electric interconnection among the chips. The through-silicon via can provide shorter route and lower resistance and inductance than line connection, which is more suitable for the transmission of signal and electricity.
However, after the through-silicon via packaging is finished, it is necessary to carry out the test of system, in order to confirm whether the packaging is correct or not. The conventional through-silicon via packaging test utilizes the Boundary-Scan (BSD) technique to test through-silicon via, as shown in FIG. 1. However, the conventional Boundary-Scan test is very complicated, which needs several sequential and combination circuits, thus it needs more space for the test. On the other hand, it needs more instructions and more time to do Boundary-Scan test. The test timing is not efficient as well.
Therefore, according to the above-mentioned drawbacks, it is necessary to research and develop an innovative through-silicon via testing structure, so as to eliminate the complicated structure and test procedure, and further reduce the test time of packaging.